The present invention relates to a memory circuit for processing a data signal, supplied from a counterpart station, into a processed signal supplied as an input signal to a signal processing circuit. The input signal is used for carrying out a predetermined processing operation in a manner known in the art.
Upon transmission from one communication device to another, it is necessary to use clock signals which have the same transmission rate and are synchronous with one another.
Referring to FIG. 1, there is shown a transmission between conventional communication devices in a communication system known in the art. A subject station SS and a counterpart station CS have the same structure and represent the communication devices. To explain transmission from the counterpart station CS to the subject station SS, a structure of only the subject station SS is shown, while a structure of the counterpart station CS and an explanation about transmission from the subject station SS to the counterpart station CS is omitted.
The subject station SS comprises a memory 1 and a signal processing circuit 2. In the communication system, the transmission from the counterpart station CS to the subject station SS is carried out at a given fixed transmission rate. In the subject station SS, a data signal S is received from the counterpart station CS and a clock signal CLK is received at the same transmission rate with and synchronous with the data signal S. These signals are used to carry out writing successively into the memory 1. The data signal S written into the memory 1 is read out successively from the memory 1 in response to the clock signal CLK and then outputted to the signal processing circuit 2. The signal processing circuit 2 processes the data signal S and writes the result of processing into the memory 1 in response to occurrences of necessity.
As the well-known techniques relating to the general clock phase synchronization and the general memory control, a clock phase synchronization device disclosed in Japanese Patent Publication (laid-open) No. 61-189042 and a memory control circuit disclosed in Japanese Patent Publication (laid-open) No. 4-297936, for example, may be cited.
In the foregoing communication system, each of the subject station and the counterpart station has, in general, an interface function corresponding only to the given fixed transmission rate and carries out transmission according to that given transmission rate. Thus, if a data signal is transmitted at other than the foregoing given transmission rate or a fluctuation in transmission rate is caused at least in one of the subject and counterpart stations, the quality of the data signal is degraded.